The present invention relates to thin-film structures such as transistors.
Wu, I-W., Lewis, A., and Chiang, A., "Effects of Solid Phase Crystallization and LDD Doping on Leakage Current Distributions in Poly-Si TFTs with Multiple Gate Structures," Digest of Japan Displays, 1992, pp. 455-458, state that, to reduce the leakage current in polycrystalline-silicon thin-film transistors (poly-TFTs), it is necessary to reduce either the trap-state density or the electric field at the drain junction. The introduction on page 455 indicates that, for poly-TFTs, solid-phase crystallization (hence grain size), gate-to-drain offset LDD structures, and multiple gate structures can be used to achieve a high level of leakage current control. The description of FIG. 2(a) on page 455 indicates that the reduction in leakage with increasing number of gates is due to a decrease of electric field strength in the drain region. On the other hand, the slopes of leakage current versus negative gate bias are not reduced for different numbers of gates. FIG. 9 shows double gate TFT ON/OFF currents with respect to LDD phosphorus implant dose for a gate-to-source/drain (S/D) offset of 1.0 .mu.m, normalized to leakage and drive current of a TFT without gate-offset regions. The lightly doped S/D reduces leakage by reducing the drain electric field.